The present invention relates to storage area networks (SAN), and in particular to virtual SANs.
Storage virtualization describes the process of representing, to a user, a number of discrete physical storage devices as a single storage pool having a single set of characteristics. For example, in a storage area network connecting host computers with storage devices, the user perceives a single block of disk space with a defined reliability (e.g., 100 GB at RAID 1), regardless of whether the data is stored on a single RAID 1 disk array or is split across multiple, separate disk arrays.
In the above situation, each host computer must be aware of the storage devices connected to the storage area network because each host computer manages the storage virtualization that is presented to its users. When the storage devices connected to the storage area network are modified (such as a new device being added or an existing device being removed), each host computer must be reconfigured to accommodate the modification. Such reconfiguration involves work by network administrators and ensures that changes in the network are not seamless.
FIG. 1 shows a schematic view of information transfer by a conventional storage area network. Specifically, conventional Storage Area Network (SAN) 20 comprises storage server 22 in communication with external data source 24 such as a minicomputer, and external data storage device 26 such as a disk array, through port 23 in communication with fibre channel (FC) controller 28.
Communication between FC controller 28 and CPU 30 of storage server 22 of SAN 20 shown in FIG. 1 takes place typically along a PCI bus 32. Conventionally, the transfer of data in and out of storage server 4 is performed utilizing a store-and-forward algorithm. Specifically, FC controller 28 sends and receives data directly to and from memory 34 of host server 22. Similarly, FC controller 28 forwards received commands to memory 34 of host server 22, interrupting operation of CPU 30 of host server 22 until all information has arrived.
Data handling techniques employed by the conventional storage area network shown in FIG. 1 offer certain disadvantages. One disadvantage of the configuration shown in FIG. 1 is the consumption of attention of the CPU of the storage server to manage operation of the FC processor. For example, TABLE 1 below lists a typical sequence of twelve steps 1-12 which occur when the FC controller responds to an FCP_CMND from a host requesting data.
TABLE 1Step#Step1FCP_CMND frame arrives2Command arrives. Interrupt is generated.3CPU interrogates the interrupt cause (command).4CPU reads memory to examine the FCP_CMND5CPU allocates memory for a Write command OR wireless data tomemory for a Read command.6CPU tells controller that buffers are available for processing.7Controller reads memory (data) and ships data out.8Transfer complete. Interrupt is generated.9CPU interrogates interrupt cause (transfer complete).10CPU writes status to memory.11CPU tells controller that the STATUS frame is in memory.12Controller reads memory (data) and ships data out.
FIG. 1 shows this flow of interaction between a FC controller chip 28 and the host CPU 30. In this case the CPU is involved with at least three memory access steps as well as accessing the FC controller through the PCI bus at least four times. The FC controller itself has to access the memory at least three times.
Further compounding the problem, the FC controller generates an interrupt. This causes the CPU to take the penalty of processing interrupts, which is heavy since a stack has to be saved into memory. When the JO traffic from the FC controller is heavy, interrupts are generated frequently; and the CPU spends a lot of time just saving the contexts.
As the CPU handles all commands, commands requiring a lot of processing block the simpler RD and WR commands that are communicated much more frequently.
The PCI bus can only have a certain amount of load. This limits the number of devices that can sit on the bus. A PCI bridge 36 can help solve this problem, but this causes latency.
The CPU in this case usually runs a real time or general purpose operating system (OS). CPU cycles are shared between the OS and IO handling. Interrupts are frequently taken by the CPU for things such as timers or serial port traffic.
Frames are processed in a “store and forward” approach. The entire frame has to be in memory before the CPU is informed of it's arrival. This further detracts from the speed of operation of the system shown in FIG. 1, as each incoming frame must first be buffered and then retrieved in order for proper routing to occur.
Still another disadvantage of the conventional approach shown in FIG. 1 is complexity, as the processor must include sufficient memory capacity in the form of buffering hardware to store the necessary quantity of information.
Another disadvantage associated with the system shown in FIG. 1 is the bottleneck created by the single FC controller, which is allocated to both receive incoming information from external hosts, and to issue commands to retrieve data from the storage devices.
FIG. 2 shows an example of a conventional virtual storage system 60 which utilizes off-the-shelf PC hardware using general Operating Systems (OS). In the implementation shown in FIG. 2, there are two separate FC controllers 28a and 28b. FC controller 28a is in communication with storage device (INITIATOR) 26 through port 63a. FC controller 28b is in communication with Host (TARGET) 24 through port 63b. 
A disadvantage of the conventional approach shown in FIG. 2, however, is that the two separate FC controllers 28a and 28b are now contending for access to memory 34, internal bus 32, and CPU 30. Both controllers 28a and 28b are also interrupting CPU 30 with work requests.
To preform virtualization, the CPU has to bind the Host that is sending the command with the LUN number in the command. The FC controller would send an identifier indicating which host sent the command. The CPU would then have to perform a hash lookup using the handle and the LUN number. The identifier used by the controller is usually a pointer to its internal device context.
With FC, the link may bounce. The FC controllers will then perform discovery again. This time however, a different identifier may be chosen by the FC controller for that same Host. The CPU would then have to modify its tables so that the correct binding will be established.
Given the disadvantages associated with conventional storage systems, embodiments of the present invention are directed toward improvements in these and other areas.